This invention relates to buck converters, and more particularly to a tapped-inductor step-down converter and method for clamping same.
The ever-present demands for faster and more efficient data processing have prompted a significant development effort in the area of low voltage integrated chips (ICs). Currently, 3.3-V ICs are gradually replacing the standard 5-V ICs due to their better speed, power consumption performance and higher integration densities. However, the 3.3-V IC is only a traditional stage to ICs with ever lower voltages that will not only improve the speed and reduce the power consumption of ICs but also will allow direct, single-cell battery operation. It is expected that next generations of the data processing ICs will require power supply with voltages in the 1-3 V range. At the same time, since more devices are integrated on a single processor chip and the processors operate at higher frequencies, microprocessors need aggressive power management. Future generation processors"" current draw will increase from 13A to 50A-100A and the load range may reach 1:100. On the other hand, as the speed of the ICs increases, they are becoming more dynamic loads to their power supplies. The next generation microprocessors are expected to exhibit current slew rates of 50A/ms. Moreover, the output voltage regulation becomes much tighter from 5% to 2%. All requirements pose very serious design challenges. Voltage regulator modules (VRMs), which feed the microprocessors, have to have high efficiency, fast transient response and high power density.
A conventional synchronized buck converter, such as shown in FIG. 1, is typically used as a VRM to meet these requirements. The conventional synchronized buck converter includes two switches S1 and S2 which are turned on and off in a complementary manner, output capacitor CO1 and load RL1. The voltage gain for the conventional synchronized buck converter of FIG. 1 is given by                     D        =                              V            ⁢                          xe2x80x83                        ⁢            o                                V            ⁢                          xe2x80x83                        ⁢            in                                              Eq        .                  xe2x80x83                ⁢                  (          1          )                    
where D is the duty ratio or cycle of switch S1. It has been well established that the conventional buck converter has better efficiency for a duty cycle D of 0.5. For an input voltage Vin of 5V and an output voltage Vo of 2V, the duty cycle D is 0.4, which is good to achieve high efficiency.
Since the future VRM should provide more power to the microprocessor, the power switch has to deal with high current, which decreases efficiency. The higher the input voltage Vin, the lower the input current so as to reduce the conduction loss. If the input voltage Vin to the VRMs increases from 5V to 12V, then the current rating for the buck switch is significantly reduced, which increases efficiency. Therefore, the VRMs would need a 12V or higher input voltage Vin. According to Severns et al., xe2x80x9cModern DC-To-DC Switch Mode Power Converter Circuits,xe2x80x9d TK7868, 1984, pg. 178, the duty cycle D for the conventional synchronized buck converter is as small as 0.15V with 12V input. This will result in poor performances in terms of voltage regulation and transient response.
FIGS. 2 and 3 illustrate a conventional tapped-inductor synchronized buck converter and the switching waveforms thereof, respectively. In operation, when switch S11 is turned on and switch S12 is turned off during time the interval T1 to T2, the voltage Vin-Vo is applied to the windings N1 and N2 of the tapped-inductor. The input voltage Vin is from a DC voltage source 2 and the output voltage Vo is across a load RL10. The conventional tapped-inductor synchronized buck converter delivers power to the output. At time T2, switch S11 turns off and switch S12 turns on. The energy stored in winding N1 is transferred to winding N2 and the winding current IN2 flows through switch S12. The voltage gain of the conventional tapped-inductor synchronized buck converter is given by                                           V            ⁢                          xe2x80x83                        ⁢            o                                V            ⁢                          xe2x80x83                        ⁢            in                          =                  D                      1            +                                          N1                                  N2                  .                                            *                              (                                  1                  -                  D                                )                                                                        Eq        .                  xe2x80x83                ⁢                  (          2          )                    
From Eq. (2), it can be readily seen that approximately a 0.5 duty cycle (D) can be obtained to achieve high efficiency by properly choosing the turns ratio of the windings N1 and N2 of the tapped-inductor. However, the main problem is that there exists a high voltage spike across switch S11 when switch S11 turns off because the leakage energy of leakage inductance Lk of winding N1 can not be transferred to winding N2. Instead, the leakage energy of leakage inductance Lk charges the output capacitor Cs1 of the switch S1 (not shown) through conducting switch S12, which causes a high voltage stress across switch S11. As a result, the high voltage rating metal-oxide semiconductor field-effect transistor (MOSFET) has to be used. The MOSFET has a high on-resistence with a high voltage rating, which significantly increases the power loss and reduces the efficiency.
FIG. 3 illustrates the switching waveforms of the switches S11 and S12, currents IS11 and IS12 and the voltage stress VS11 and VS12 across switches S11 and S12, respectively.
As can be readily seen, there is a continuing need to improve the VRM performance to meet these requirements.
Broadly, the present invention contemplates a tapped-inductor step-down converter and method for clamping same so that low voltage rating MOSFETs can be used to improve the efficiency of the converter. The converter includes a tapped-inductor and a clamping capacitor which are uniquely arranged to recycle the leakage energy from a leaky inductance of the tapped-inductor and to eliminate resonance between the leakage energy of the leaky inductance and the clamping capacitor.